Vapor phase connection techniques

ABSTRACT

Electrical connections are made between a pair of elements disposed on opposite side of the hole extending through a dielectric layer by evaporating a conductive material such as a metal having high vapor pressure within the hole while maintaining the hole in a substantially sealed condition. The process may be performed simultaneously to form numerous connections within a microelectronic unit as, for example, within a multilayer circuit panel.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a divisional application of U.S.patent application Ser. No. 09/636,790, filed Aug. 11, 2000, whichapplication claims benefit of U.S. Provisional Patent Application SerialNo. 60/148,233, filed Aug. 11, 1999, the disclosures of which are herebyincorporated by reference herein.

FIELD OF THE INVENTION

[0002] The present invention relates to microelectronic components andfabrication of microelectronic components.

BACKGROUND OF THE INVENTION

[0003] Numerous microelectronic components incorporate insulating or“dielectric” layers and conductors extending through such layers. Thedirections along the surfaces of the layers are commonly referred to as“horizontal” directions, whereas the direction through the layers iscommonly referred to as the “vertical” or “z” direction. The conductorsextending through the layers are commonly referred to as z-directionconductors or “vias.” For example, a multilayer microelectronic circuitpanel may include several dielectric layers. Each dielectric layer hasconductors extending along one or both surfaces of the layer inhorizontal directions and has vias extending through the layer toconnect certain conductors on opposite sides of the panel with oneanother. Typically, such a multi-layer circuit is fabricated by asequential process. Each dielectric layer is deposited onpreviously-formed dielectric layers and the processes needed to form thevias and the horizontal conductors are performed. Such a sequentialbuild-up process suffers from numerous drawbacks, including significantloss of productivity caused by quality problems. If any defect occurs information of a later layer, the entire multi-layer structure must bediscarded.

[0004] As taught in certain preferred embodiments of commonly assignedU.S. Pat. Nos. 5,367,764 and 5,282,312, multi-layer circuit panels canbe fabricated using a parallel-processing approach. In this approach,the various panels constituting the multi-layer structure are fabricatedseparately and then stacked together with interposers incorporating acurable dielectric material such as an epoxy and also incorporatingmasses of electrically conductive joining material such as solderextending through the interposer at predetermined locations. The stackedassembly is then cured as, for example, under heat and pressure. Thedielectric material joins the circuit panels to one another and theelectrically conductive material forms conductive pathways betweenconductors on the various panels. Because the individual panels can betested prior to assembly, defects in the panel manufacturing process donot result in loss of the entire assembly. Also, as further explained inthe aforementioned U.S. Pat. Nos. '764 and '312, the individual panelscan be selectively treated so that vertical connections between panelsare made only at certain locations.

[0005] Other processes involving parallel production of multiple circuitpanels and assembly in a stack are taught in certain preferredembodiments of co-pending, commonly assigned PCT ApplicationPCT/US97/23948, published as International Publication WO 98/26476 andU.S. Pat. No. 5,590,460. As taught in certain preferred embodiments ofthe U.S. Pat. No. '460 and '948 PCT application, multiple circuit panelscan be stacked and electrically interconnected with one another andmechanically engaging features on the circuit panels with features ofconductive elements carried on interposer layers.

[0006] These approaches offer useful solutions to the encountered infabrication of multi-layer problems. However, even with theseimprovements, the circuit panels typically still include vias extendingthrough dielectric layers. Such vias commonly are formed by providingholes in the dielectric layers and depositing a conductive metal in thedielectric layers by processes such as electroless plating andelectroplating. These processes work well with relatively large vias.However, it would be desirable to provide smaller vias so as to make theentire assembly more compact. It is difficult to form relatively smallvias, such as circular vias having diameters less than about 60 micronsand, more particularly, less than about 25 microns by plating.

[0007] Various proposals have been advanced for depositing conductivematerials into holes to form vias by techniques other than plating.Cranston, et al., U.S. Pat. No. 3,562,009 shows a process for forming“metalized through-holes” by positioning a metallic element at a lowersurface of a substrate having a hole formed therein and directing alaser beam or electron beam from above the substrate through the opentop end of the hole onto the metal, thereby evaporating the metal ontothe walls of the hole. In other embodiments, this reference disclosesdirecting a similar beam onto a mass of powdered material disposedwithin the hole. This method suffers obvious drawbacks as a productiontechnique, including the need to direct a powerful beam sequentiallyonto various locations on the substrate and hold the beam at eachlocation for a time sufficient to vaporize the material. Moreover, thismethod is useful only to process a single substrate at a time. Beilin,et al., U.S. Pat. No. 5,454,161 discloses metal organic chemical vapordeposition (“MOCVD”) of metal into openings of a dielectric layer. Inthe MOCVD process, the substrate is held in the reaction chamber so thatopenings of the holes are exposed to the interior of the reactionchamber. A metal-containing gaseous composition is introduced into thechamber. The composition decomposes to deposit metal in the open vias.Yamaguchi, et al., U.S. Pat. No. 5,589,668, discloses a similar processusing vapor deposition methods such as evaporation, ion plating, orsputtering. In all of these processes, the substrate is held within achamber so that openings of the vias are open to the interior of thesubstrate. Each substrate must be held within a relatively complex andexpensive treatment apparatus for a time sufficient to build up therequired metallic layer within its vias. Moreover, stacked substratescannot be treated. U.S. Pat. No. 4,933,045 refers to metalization ofvias by “evaporation, sputtering or plating” as assertedly “well-knownin the art” but does not offer further details of such processes.Despite these attempts to use vapor deposition for forming vias, thereis still need for better useful and economical vias-forming process.

[0008] Another common problem encountered in fabrication ofmicroelectronic assemblies is mounting and connecting one component toanother. For example, a semiconductor chip or other microelectronicdevice typically must be connected to a circuit panel. As described incertain preferred embodiments of commonly assigned U.S. Pat. Nos.5,148,265, 5,148,266 and 5,347,159, the contacts of a semiconductor chipmay be electrically connected to terminals on a small circuit panel orconnection component overlying a face of the chip itself. The terminalson the connection component in turn are connected to contact pads on asubstrate such as a circuit panel. Desirably, the connection componentis movable with respect to the chip to accommodate dimensional changescaused by thermal effects during manufacture and/or use. The connectionsbetween the chip contacts and the interposer can be made by variousmethods. For example, these connections can be made by wire-bonding orby techniques such as thermosonic or ultrasonic bonding ofpre-fabricated leads on the interposer to the chip contacts. Furtherimprovements in lead bonding are taught, for example, in U.S. Pat. Nos.5,536,909, 5,787,581 and PCT International Publication No. 94/03036.These processes provide marked improvements in chip connection processesand in the resulting assemblies.

[0009] In a process known as flip-chip bonding, contacts on the chip arebonded directly to contact pads on a substrate such as a circuit boardusing solder balls. All of the contacts of the chip may be connectedsimultaneously. However, flip-chip bonding requires considerable spacingbetween contacts on the chip to accommodate the solder balls and suffersfrom other drawbacks including susceptibility to thermal stresses.

[0010] As described in U.S. Pat. No. 5,518,964, numerous connections ona semiconductor chip or wafer can be made simultaneously by superposingan element such as a dielectric substrate having leads thereon with thechip or wafer bonding tip ends of the leads to the contacts on the chipand moving the element away from the chip or wafer so as to deform theleads. The resulting structure provides compensation for thermal effectsand provides a high-reliability interconnection with the chip.Nonetheless, it would be desirable to provide even further improvementsin methods for connecting components to one another.

[0011] Kim, U.S. Pat. No. 5,407,864 proposes mounting a chip on onesurface of a circuit panel so that the contacts of the chip face downonto a top surface of a circuit board. The contacts on the chip arealigned with through-holes extending through the circuit board, to thebottom surface thereof. A metal is deposited through the openings of thethrough-holes at the bottom surface, as by sputtering, screening,electroplating or evaporation, so that the deposited metal formsconductive extensions of the chip contacts extending through the holesto conductors on the circuit board. This method suffers from the obviousdrawback that holes must extend through the circuit board at each chipcontact location. This, in turn, makes it impractical to mount a chiponto a multi-layer circuit panel. Moreover, where the process isperformed using an evaporative technique, the structure, including thechip and the circuit panel must be retained in the evaporation apparatusfor the full time required to deposit the metal. Additionally, theresulting structure has no ability to take up differential expansion andcontraction between the chip and the circuit panel. Thus, despite all ofthe effort in the art presented by the aforementioned patents andpublications, further improvements in via formation and connectiontechniques would be desirable.

SUMMARY OF THE INVENTION

[0012] One aspect of the present invention provides a method of makingconnections in a microelectronic unit. A method according to this aspectof the invention includes the step of providing first and secondconductive elements and a dielectric so that the dielectric and theconductive elements cooperatively define a substantially closed chamber.A dispersible conductive material, such as a metal having appreciablevapor pressure is also provided within the chamber. For example,low-melting metals such as tin, gallium, silver, indium and alloysthereof may be used. Other low-melting alloys include alloys containingone or more of tin, bismuth and antimony. The method further includesthe step of dispersing the conductive material within the substantiallyclosed chamber so that the conductive material deposits on thedielectric and forms a connector extending between the conductiveelements. Most preferably, the step of dispersing the conductivematerial is performed by evaporating the conductive material within thechamber. The chamber desirably is maintained under subatmosphericpressure. Alternatively or additionally, the atmosphere within thechamber may consist essentially of one or more inert gases, mostpreferably argon. The dielectric, the conductive elements or bothmaintain the chamber substantially isolated from the surroundings duringthe dispersing step, so that the dispersing step occurs withoutappreciable transfer of the conductive material into the chambers duringthe dispersing step. Stated another way, the conductive material alreadypresent within the substantially closed chambers is dispersed in situ.Most preferably, the substantially closed chamber is sealed gas-tight bythe conductive elements, the dielectric or both.

[0013] The step of providing first and second conductive elements and adielectric may include providing a dielectric layer having oppositelydirected first and second surfaces and having one or more holesextending through the layer between the surfaces, and providing thefirst and second conductive elements so that they overlie the hole onthe first and second surfaces of the dielectric layer. For example, thefirst conductive elements, the second conductive elements or both may beprovided on separate bodies bearing these elements. These bodies may belaminated onto the dielectric layer, thereby forming one or morechambers as discussed above. The conductive material may be provided onthe conductive elements as, for example, by depositing the conductivematerial through one or more techniques such as electroplating,electroless plating, sputtering, evaporation and chemical vapordeposition.

[0014] Once the chamber or chambers is or are closed, the process ofevaporation simply requires maintaining the assembly at a suitabletemperature for a sufficient time to allow the conductive material toredistribute itself within the chambers by evaporation. The assembly maybe maintained under an external, surrounding subatmospheric pressure as,for example, by holding the assembly within a temporary housing orstorage bin held at subatmospheric pressure so as to minimize mechanicalstress on the assembly and minimize diffusion into the chamber orchambers. However, there is no need to maintain the assembly withinspecialized processing apparatus during the evaporation process. Theevaporation process may occur, for example, within a simple oven orholding fixture.

[0015] Numerous connections can be formed simultaneously using thesemethods. For example, hundreds or thousands of connections can be formedbetween individual conductive elements of an assembly during a singleevaporation step. The process is inherently reliable; provided that theconductive material is present and the conductive elements are exposedto the interior of the chamber, the conductive material will form aconductor connecting the conductive elements. Moreover, the evaporationprocess can be repeated after the assembly is tested to repair anydefects detected during testing operation. If an assembly has defects,the assembly is simply recycled into the heating step, without furtherprocessing. Unlike conventional via-forming processes such aselectroplating, the process according to this aspect of this inventionworks best with small holes. For example, holes having cross-sectionaldimensions on the order of 60 micrometers or less, and more preferably25 micrometers (about 0.001 inches) or less may be used successfully.The process thus lends itself well to fabrication of extremely compact,high density circuits.

[0016] A further process according to this aspect of the inventionincludes the step of providing a first dielectric layer having first andsecond surfaces and having a plurality of holes extending through suchlayer between the first and second surfaces and providing firstconductive elements adjacent the first surface and second conductiveelements adjacent to second surface so that these conductive elementsare aligned with at least some of the holes. For example, the step ofproviding the first conductive element may include providing a firstbody having the conductive elements thereon juxtaposed with firstsurface of the dielectric layer. The second conductive elements may beprovided on a similar, second body juxtaposed with the second surface ofthe dielectric layer. A method according to this aspect of the inventiondesirably further includes the step of providing a conductive materialin at least some of the holes which have the first and second conductiveelements aligned therewith and dispersing the conductive materials,preferably by evaporating the conductive materials, so as to formconductors interconnecting the first and second conductive elementswhich are aligned with at least some of the holes.

[0017] The process can be used to provide connections to a semiconductorchip or other microelectronic element having contacts on a frontsurface. Thus, the first body used in the aforementioned process may bea chip, an assemblage of plural discrete chips or an integral waferincorporating numerous semiconductor chips. The dielectric layer may beprovided on the contact-bearing front surface of the chip, assembly orwafer as by applying a curable adhesive to the front surface and bondinga preformed dielectric layer onto the adhesive or by applying thedielectric layer as a coating and curing and curing the coating. Theholes may be formed in the dielectric layer in alignment with thecontacts either before or after applying the dielectric later to thefront surface. In this arrangement, the contacts on the microelectronicelement serve as the first conductive elements. The second conductiveelements may be provided on a circuit panel or other mounting substrate.In certain embodiments, the second conductive elements may includeelongated conductors having fixed ends and free ends. The fixed ends arealigned with at least some of the holes in the dielectric element. Thefree ends of the leads may be displaceable relative to the dielectriclayer so that a second microelectronic element may be attached to thefree ends of the elongated conductors and moved away from the dielectriclayer so as to deform the conductors. Alternatively, the dielectriclayer may include elongated lead regions having fixed ends and havingfree ends displaceable with respect to the remainder of the dielectriclayer. At least some of the conductors desirably extend along theseelongated lead regions so that the free end of each such elongatedconductor is disposed adjacently free end of an associated lead region.Here again, a further microelectronic element may be assembled to thefree ends of the leads and moved away from the first microelectronicelement and dielectric layer to deform the leads. As further discussedbelow, such processes can provide semiconductor chip packages andmountings with the ability to take up relative movement caused bythermal effects.

[0018] At least one of the steps of providing first conductive elements,providing second conductive elements, and providing conductive materialmay be performed selectively so that the first conductive element, thesecond conductive element, or the conductive material is omitted atleast some of the holes and hence no connection is made between firstand second conductive elements at those holes. The process therefore canbe used to form connections selectively. As discussed below, selectiveformation of conductive elements and/or selective application ofconductive material can be achieved readily using known techniques suchas selective plating or etching, screen printing and selective vapordeposition, as for example, using a mask to block vapor deposition inareas where deposition is not wanted.

[0019] According to a further variant, the process may incorporate thestep of providing a stacked structure including one or more dielectriclayers and plural layers of conductive elements separated from oneanother by these one or more dielectric layers. At least some of theconductive elements in different layers are aligned with one another atone or more sites and the dielectric layers have holes extending throughthem between the aligned conductive elements at at least some of thesites. Here again, a dispersible conductive material such as theaforementioned high-vapor pressure metals is supplied at at least someof the sites. After the stacked structure has been made, the conductivematerial is evaporated onto the walls of the holes in the dielectriclayers to thereby form vertical connections between conductive elements.The conductive metal may be evaporated within holes in all of thestacked layers simultaneously.

[0020] The vertical connections are formed at only those sites where theconductive elements are aligned with one another; where the dielectriclayer which is disposed between these aligned conductive elements has ahole in alignment with the conductive element and where the conductivematerial is provided. This method is particularly well-suited tomanufacture of multi-layer circuitry. Thus, the one or more dielectriclayers typically includes numerous dielectric layers. The verticalconductors extending through the stacked structure can be providedselectively by conducting any one of several steps selectively. Forexample, the step of providing holes in the dielectric layers may beperformed selectively so that holes are provided at less than all of thesites. The holes may be disposed at locations of a regular grid pattern,but less than all of such locations may be provided with holes. Also,the step of applying the evaporable conductive material may be performedselectively. For example, where the conductive material is applied ontothe conductive elements before stacking as, for example, where theconductive material is applied by plating, the conductive material maybe applied selectively by masking areas where conductive material is notwanted before plating or by selectively etching away the conductivematerial using an etchant which does not attack the conductive elementssubstantially. Stated another way, the operations required to provideconductive material in a selective manner to less than all of the sitesmay involve only conventional procedures commonly used for applyingmetals in a controlled fashion in microelectronic circuit processing.

[0021] The layers of conductive elements may include first direction andsecond direction layers arranged in alternating order. The conductiveelements in each first direction layer include elongated tracesextending predominantly in a first horizontal direction whereas theconductive elements in each second direction layer have elongated tracesextending predominantly in a second horizontal direction transverse tothe first horizontal direction. The holes are desirably arranged at atleast some locations of a regular grid pattern corresponding to crossingpoints of the first direction and second direction traces. Such anarrangement provides complete flexibility in layout of the circuit.Moreover, because very small vias can be employed, there is no need toprovide enlarged features at the crossing points.

[0022] In further variants, the conductive material may be dispersedwithin the chambers by processes which do not entail evaporation as, forexample, by applying sonic energy to atomize the conductive material ina liquid state or to mechanically spread the liquid conductive material.Here again, the process desirably does not rely upon filling of thechamber or via with liquid. In still other variants, a conductivematerial precursor is provided within the closed chambers and reacts toform a conductive material within the closed chambers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a diagrammatic perspective view depicting certaincomponents used n one embodiment of the invention.

[0024]FIG. 2 is a diagrammatic sectional view depicting the componentsof FIG. 1 during an assembly procedure in accordance with one embodimentof the invention.

[0025]FIG. 3 is a diagrammatic sectional view depicting components inaccordance with a further embodiment of the invention.

[0026]FIG. 4 is a diagrammatic sectional view depicting the componentsof FIG. 3 in conjunction with another element during a later step of theprocess.

[0027]FIG. 5 is a diagrammatic top plan view depicting a component inaccordance with yet another embodiment of the invention.

[0028]FIG. 6 is a diagrammatic sectional view taken along line 6-6 inFIG. 5.

[0029]FIG. 7 is a view similar to FIG. 6 but depicting the component inconjunction with another element during a later stage of a manufacturingprocess.

[0030]FIG. 8 is a fragmentary, diagrammatic sectional view depictingcomponents in accordance with another embodiment of the invention.

[0031]FIG. 9 is a diagrammatic elevational view of the components shownin FIG. 8.

[0032]FIG. 10 is a diagrammatic elevational view depicting components inaccordance with a further embodiment of the invention.

[0033]FIG. 11 is a fragmentary, partially-sectional perspective viewdepicting components in accordance with yet another embodiment of theinvention.

[0034]FIG. 12 is a diagrammatic, partially-exploded view depictingcertain components during a process according to a further embodiment ofthe invention.

[0035]FIG. 13 is a diagrammatic sectional view depicting components usedin a further embodiment of the invention.

[0036]FIG. 14 is a fragmentary, diagrammatic sectional view depictingcomponents and process equipment during a method according to yetanother embodiment of the invention.

[0037]FIG. 15 is a diagrammatic elevational view depicting componentsand process equipment during a method according to a still furtherembodiment of the invention.

[0038]FIG. 16 is a fragmentary, partially sectional elevational viewdepicting an assembly according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] A process in accordance with one embodiment of the inventionutilizes a set of bodies 20 of a first type and bodies 22 of a secondtype. Each body 20 includes a sheet-like dielectric layer having a topsurface 24 and an oppositely directed bottom surface 26. In theparticular embodiment illustrated, each layer 20 is formed from a sheetof polyamide approximately 25-100 microns thick. Each of the bodies orlayers 20 has a coating or sublayer 21 of a heat-curable bondingmaterial on its bottom surface. Bonding material layer 21 may beintegral with body or layer 20 or else may include a distinct adhesivediffering in composition from the remainder of the body or layer 20.Suitable adhesives include those commonly used in manufacture oflaminated flexible circuits for high-temperature service, such aspolyamides, epoxies and cyanate-PTFE materials.

[0040] Each layer 20 also has holes 28 extending through it, from itstop surface 24 to its bottom surface 26. These holes are arranged atlocations of a regular, rectilinear grid pattern having columns of holesextending in a first or x horizontal direction and having rows of holesextending in a second or y horizontal direction orthogonal to the firstor x-direction. The holes need not be provided at every location of theregular grid pattern. For example, one hole is omitted at a location 30within the grid pattern. Although only a few holes are depicted in FIG.1 for clarity of illustration, in practice a typical layer may havetens, hundreds or thousands of holes and may have omitted holes at manylocations of the regular grid patterns.

[0041] Desirably, each hole is less than about 60 microns in diameter,more preferably less than about 25 microns in diameter and mostpreferably about 12.5 microns in diameter or less. The dielectric layers20 may be solid dielectric. Alternatively, some or all of the dielectriclayers in bodies 20 may incorporate conductive elements disposed in theinterior of the dielectric layers. For example, body 20 b includes aninternal electrically conducive potential plane 36 disposed between thetop and bottom surfaces of the dielectric layer. As shown in FIG. 2,potential plane 36 is isolated from most of the holes 28 in this layer.However, the potential plane 36 extends to one or a few holes 28 b inlayer 20 b. As explained below, conductive layer will form connectionsto a vertical via at hole 28 b.

[0042] Each layer 20 also includes traces 32 extending along the topsurface of the layer. The traces 32 on bodies 20 extend predominantly inthe first or x direction, although some portions of the traces extend inother directions as well. Here again, the trace pattern is greatlysimplified for clarity of illustration. A typical pattern of traces willinclude hundreds of traces. Also, traces may be broken or continuous.For example, trace 32 a has a break 34 at one location. At least some ofthe traces 32 extend over the top ends of holes 28. Stated another way,the traces extend over locations of the regular grid pattern of theholes.

[0043] The holes and traces can be formed by essentially anyconventional technique used in fabrication of microelectronic circuitpanels. For example, the traces can be formed by subtractive etchingfrom a sheet of copper or other conductive metal overlying the topsurface of the body by using a photoresist or other patternable maskingmaterial to control the etchant process and leave the undesired traces.Alternatively, the traces can be formed by conventional additiveplating. The holes may be formed by laser ablation or chemical etchingof the dielectric layer again using a photoresist or other mask.Alternatively, the dielectric layer itself may be formed from aphotosensitive dielectric and the holes may be formed by selectiveexposure and curing of the dielectric.

[0044] Dielectric bodies 22 of the second type are essentially the sameas bodies 20. Each body 22 has a top surface 23, a bottom surface 25,and a curable bonding material 27 on its bottom surface 25. Each body 22has holes 39 extending through it. The traces or conductors 38 on layers22 extend predominantly in the second or y horizontal direction. Spotsof a high vapor pressure conductive metal 40 are disposed on the topsurfaces of traces 38. Similar spots of conductive metal 42 are disposedon the top surfaces of the traces 32 of first-direction layers 20. Thespots 40 and 42 are disposed in regular grid patterns with spacing inthe first and second horizontal directions equal to the spacing used inthe regular grid pattern of the holes. The spots of high vapor pressureconductive material are omitted from body 20 a, which will form the toplayer in the stack.

[0045] In an assembly process according to one embodiment of theinvention, bodies 20 having leads extending in the first or x directionare stacked in alternating order with bodies 22 having traces extendingin the second or y direction. The grid of conductive material spots 40on each second-direction body 22 is aligned with the grid of holes 28 inthe next higher first-direction layer 20 in the stack. For example, thegrid of conductive material spots 40 on second-direction layer 22 a isaligned with the grid of holes 28 in the next higher layer 20 a.Similarly, the grid of conductive material spots 32 on first-directionlayer 20 b is aligned with the grid of holes 39 in the overlyingsecond-direction layer 22 a. The layers are disposed in a vacuumlamination apparatus having an enclosed chamber and having a pair ofopposed platens inside the chamber. The chamber is flushed with an inertgas and brought to a substantial vacuum. This process is repeated toassure that the holes in all of the layers have been substantiallyflushed with the inert gas, and then the chamber is brought to a lower,subatmospheric pressure desirably about 200 Torr or less and moredesirably about 10 Torr or less. Still lower pressures, of about 1 Torror less can be used. During the flushing and the evacuation process, thelayers may be held apart from one another by temporary spacers (notshown) to assure good communication between each of the holes and thesurrounding atmosphere within the chamber. Alternatively, the flushingand the evacuation process can be performed before the layers arestacked on one another.

[0046] After the flushing and evacuation procedure, the layers arelaminated to one another under heat and pressure applied by squeezingthe layers between the platens. The bonding materials 21 and 27 on thebottom surfaces of layers 20 and 22 are activated so as to bond thelayers to one another and close the holes 28 and 39 in the variouslayers. Thus, after the lamination step, hole 39 a has a firstconductive element (trace 32 b on layer 20 b); a second conductiveelement (trace 38 a at the top surface of layer 22 a) and a dielectric(the dielectric of layer 22 a) cooperatively defining a substantiallyclosed, sealed chamber, and has a conductive material 42 disposed withinsuch chamber. The same arrangement is present at at least some of theother holes 39 and 28. Desirably, the joints between the layers aregas-tight, so that each hole is sealed. At this point, the atmospherewithin each hole consists essentially of inert gas at a lowsubatmospheric type of pressure corresponding to the pressure used inthe vacuum chamber during the lamination step.

[0047] After lamination, the assembly is maintained at an elevatedtemperature for a time sufficient to evaporate some or all of the metalin spots 40 and 42. The upper limit of the temperature used in thisstage of the process should not exceed the degradation temperature ofthe materials constituting bodies 20. For example, typical polyamidesdegrade at temperatures of about 350-400° C. Also, the pressure withinthe sealed chambers defined within the bodies increases withtemperature. The temperature used in this stage should not be so high asto raise the pressure above the pressure prevailing on the exterior ofthe laminate. Thus, the internal pressure within the sealed chambersshould not exceed atmospheric pressure when the assembly is maintainedunder normal atmospheric pressure during this stage of the process.Where the bodies include organic polymers, the degradation temperatureof the polymer normally controls. The evaporated metal deposits as acoating on the interior walls of holes 28 and 39, and forms electricallyconductive vias or vertical, z-direction conductors 50 extending throughthe various layers at the holes. The vertical conductors join theconductive elements or traces bounding the various holes and thus formsvertical conductive paths through the stacked structure. For example,one such vertical conductive path extends almost entirely through thestack, from trace 32 a at the top of layer 20 a downwardly through hole28 a, hole 39 a and so on through other holes to trace 32 c at the topof the lowermost layer 20 d. Where the bodies 20 and 22 incorporateinternal conductive features extending to the holes, the conductive vialiners 50 also form connections with such internal conductive features.For example, potential plane element 36 is electrically connected to thevertical conductor at hole 28 b.

[0048] The vertical conductive paths are provided selectively. Thus, avertical via or conductive path through an individual layer is providedonly where three conditions are met: First, there must be a hole at suchlocation; no path is formed at location 30 where a hole is omitted.Second, there must be traces or conductive elements adjacent both endsof the hole. For example, no trace overlies the top end of hole 39 c inlayer 22 c near the bottom of the stack. Therefore, no verticalconnection will be formed at this hole. Third, the evaporable conductivematerial must be present within the hole. For example, at hole 39 d, noconductive material is provided and hence no vertical connection will beformed. Thus, the formation of vertical connections can be controlled byproviding holes selectively; by providing conductive elementsselectively and by providing the evaporable conductive materialselectively, as well as by any combination of these measures.Additionally, the locations and extent of vertical and horizontalconductive pads through the stacked assembly can be controlled byselective formation or interruption of the traces or conductive padsalong the surfaces of the bodies. For example, a break 52 in a trace 38on the top surface of layer 22 a electrically isolates trace 32 c on thetop surface of layer 20 a from trace 32 d on the top surface of layer 20b. Stated another way, customization of the traces on the individuallayers can provide customization of vertical path formation even withoutselective formation of the vertical conductive themselves. The use ofhorizontal-conductor customization to provide selectivity in verticalpath formation is described in greater detail in U.S. Pat. Nos.5,282,312 and 5,367,764 the disclosures of which are hereby incorporatedby reference herein.

[0049] To assure reliable connections between the conductive elements,the conductive elements should be substantially free of contaminants,particularly oxides, which may interfere with formation of a good, lowresistance joint between the deposited conductive material and theconductive element or trace. Where the traces are formed from a reactivemetal such as copper, they will typically have an oxide layer. The oxidelayer can be removed by baking in a atmosphere having very low partialpressure of oxygen as, for example, by holding the bodies bearing theconductive elements in a vacuum chamber at an elevated temperature.These procedures are similar to the deoxidizing procedures employed forflux-free soldering. Alternatively or additionally, the reactive metalmay be covered with a non-reactive metallic surface coating such as agold layer. Typically, a gold layer is applied over a coating of nickel.

[0050] During the evaporation step, the assembly need not be maintainedbetween the platens of the lamination process. Thus, each assembly canbe laminated in a brief heating and pressing operation and thentransferred to an oven for the evaporation operation. The assemblies canbe handled in bulk in the evaporation operation, without need for anyparticular fixturing other than that required to avoid mechanical damageto the exterior surfaces of the assemblies. Therefore, large numbers ofassemblies can be held in the evaporation operation. The processtherefore can achieve substantial throughput even if the dwell time inthe evaporation operation is substantial. Typically, dwell times from afew minutes to a few hours are sufficient to form the verticalconductors. Preferably, the evaporation operation is conducted in air atatmospheric pressure or even at superatmospheric pressure, so that thepressure outside of the laminate balances or exceeds the pressuredeveloped inside the sealed chambers.

[0051] Alternatively, the evaporation operation can be conducted undersubatmospheric pressure and in an atmosphere consisting essentially ofan inert gas. This assures that even if an assembly has a leakage pathto a particular hole, that hole will retain its low pressure, inert gasatmosphere. When this alternative is employed, the assembly may be heldbetween platens to assure that excess internal pressure does not causedelamination. In a further alternative, the bodies and conductiveelements may be provided with small openings so that the interiors ofthe chambers communicate with the exterior of the assembly during theevaporation operation. In this case, the evaporation operation should beconducted with an atmosphere surrounding the exterior of the assemblyunder a subatmospheric total pressure. Even in this case, however, thechambers remain substantially closed, and the process is conductedwithout appreciable transfer of conductive material into the chambersfrom outside of the assembly, and typically without any transfer ofconductive material into the chambers during the process of distributingthe conductive material within the chambers.

[0052] In the process discussed above, the vertical conductors areformed in numerous layers simultaneously. However, the process can bevaried so as to form vertical conductors in different layers seriatim.Thus, a first set of closed chambers can be formed by stacking a firstset of parts, and the conductors can be formed in those chambers. Then,one or more additional layers are added to form further chambers, andthe conductor-forming steps are repeated. This cycle of operations canbe repeated add still more layers and form more conductors, until thedesired number of layers have been added.

[0053] A process according to a further embodiment of the inventionbegins with a semiconductor wafer 100 having contacts 102 on a first orfront surface. The wafer desirably also has passivation layer 104overlying the front surface except at contacts 102. The waferincorporates internal electronic devices (not shown) electricallyconnected to contacts 102.

[0054] Contacts 102 are treated to provide a good electrical connectionwith the material to be evaporated in later stages of the process andalso to prevent undesired reactions between the conductive metal to beevaporated and the material of the contacts. For example, the zincatedaluminum contacts may be covered with a layer of nickel followed by anover-coating of gold. Following this procedure, a high vapor pressureconductive metal 103 is applied onto contacts 102 using a conventionaldeposition process such as sputtering or evaporation. Desirably, a maskis used during the sputtering or evaporation process so that theconductive material is deposited only on contacts 102. Other methods ofapplying the high vapor pressure metal can be employed. For example, thehigh vapor pressure metal can be applied by depositing balls of themetal onto the contacts and melting the metal, using the same techniquesas employed in application of conventional solder balls. Also, the highvapor pressure metal may be applied by contacting the front face of thewafer with the metal in liquid form, using a technique similar to wavesoldering. The techniques taught in copending, commonly assigned U.S.Provisional Patent Application Serial No. 60/123,602 the disclosure ofwhich is hereby incorporated by reference herein for application ofbonding materials such as solders can be used for application of thehigh vapor pressure materials. In yet another alternative, a separatesubstrate layer bearing the high vapor pressure material may be appliedover the front face of the wafer.

[0055] In the next stage of the process, a dielectric layer 106 islaminated over the passivation layer 104. Layer 106 has an adhesivelayer 108 similar to the adhesive layers discussed above on a bottomsurface and has holes 110 extending through and between its top andbottom surfaces. Layer 106 also has elongated leads 112 on its topsurface. Each lead has a first or fixed end 114 overlying one of theholes 110 and a free or tip end 116 remote from such hole. Each leadcarries a bonding material 118 such as a solder, eutectic bonding alloyor the like. The tip end 116 of each lead desirably is releasablyattached to the top surface of layer 106, whereas the fixed end 114 ofeach lead desirably is securely attached to layer 106. Lead structuressuitable for this purpose are disclosed in commonly assigned U.S. Pat.Nos. 5,518,964; 5,904,498 and in co-pending, commonly assignedInternational Published Application No. PCT/US99/02748 and U.S. patentapplication Ser. Nos. 09/020,750 and 09/195,371 the disclosures of whichare hereby incorporated by reference herein. For example, as disclosedin the aforementioned U.S. Pat. No. '498, the lead sections may havediffering bond strengths on different portions of the top layer. As setforth in certain preferred embodiments of the U.S. Pat. No. '518 and incertain preferred embodiments of the aforesaid PCT and U.S.applications, the tip end of the lead may be connected to the supportingdielectric by a small metallic or dielectric element which can be brokenor dislodged readily.

[0056] Layer 106 is laminated to wafer 100 using gas flush and vacuumlamination techniques similar to those discussed above in connectionwith formation of the stacked assembly. Thus, after lamination, thedielectric layer 106, with its cured adhesive layer 108 forms agas-tight seal to the wafer. Each hole 110 is sealed by the dielectriclayer, by the fixed end 114 of the overlying conductor 112 and by thewafer and contact 102 itself. Each holes contains an inert gasatmosphere at a low subatmospheric pressure as discussed above. Again,the assembly is held at an elevated temperature so as to evaporate theconductive material 103 from each contact 102 and to the interior of thehole 110 and thereby form a vertical connector extending between thecontact and the fixed end 114 of the associated lead.

[0057] After the vertical conductors have been formed so as to connectleads 112 to the contacts 102 of the wafer, the wafer is engaged with afurther element 122 having pads 124 exposed on a bottom surface 126.Merely by way of example, the further element may be a single-layer ormulti layer stricture having terminals 128 exposed at the top surface130. Pads 124 are bonded to the tip ends 116 of the leads by activatingthe bonding material 118 carried on the tip ends of the leads.Typically, the bonding material is activated by engaging the componentsunder heat and pressure. After the tip ends of the leads have beenbonded to the pads 124, element 122 is moved away from wafer 100 andaway from dielectric layer 106 through a predetermined verticaldisplacement. These components may also move relative to one another ina horizontal direction. Movement of these components relative to oneanother bends the leads towards a vertically extensive disposition.During or after movement of the components, a flowable, curablecomposition is introduced between the components and cured to form adielectric, desirably compliant layer 132 surrounding leads 122. Forexample, the curable material may be introduced under pressure betweenthe components and may help to impel the components away from oneanother. Techniques for performing the lead bonding and movementoperations are described in the aforementioned patents and publications.

[0058] The resulting assembly is then severed by cutting both component122 and wafer 100 along cutting planes 134 so as to thereby form aplurality of individual units. Each unit includes one semiconductor chipor a few chips in the wafer and a portion of element 122. As describedin greater detail in the aforementioned patents and publications, such aunit can be mounted on a substrate such as a printed circuit board withterminals 128 bonded to the substrate. Leads 112 can flex and compliantlayer 132 can deform so as to permit differential thermal expansion ofthe chip and circuit board without imposing significant stresses on thesolder joints between the terminals 128 and the circuit board. In othercases, the additional unit 122 itself may be a circuit board or othermicroelectronic device. The flexible leads and compliant layer providesimilar benefits in these cases. The evaporation technique provides aneffective, economical and reliable way of making connections betweenleads 112 and contacts 102. In a variant of this approach, conductivematerial 103 may be provided on the bottom surfaces of lead fixed ends114, within holes 110, and evaporated so as to form connections to thecontacts 102 of the chip. Also, bonding material 118 may be carried onpads 124 rather than on the tip ends of the leads.

[0059] In a further variant, (FIGS. 5-7) dielectric layer 206 hasnumerous generally U-shaped slots 250 extending through it andsubdividing the dielectric layer into a main region 251 and a pluralityof elongated lead regions 252. Holes 210 are formed in the main region251 of the sheet adjacent to each lead region. Elongated conductors 212extend from the main region of the sheet onto each lead region 252. Eachsuch conductor overlies one hole 210 and has a bonding material 218 atthe tip end of the lead region, remote from the main region. Theconductive, evaporable material 203 is provided on the undersides ofconductors 212, within holes 201. The adhesive layer 208 used to securedielectric layer 206 to the front surface of wafer 200 is aUV-degradable or other radiation degradable adhesive material. Thelamination and evaporation steps are performed in substantially in thesame way as discussed above so as to form vertical conductors 220connecting contacts 202 with conductors 212. Before, or more desirably,after the evaporation step, adhesive layer 206 is selectively degradedin regions 256 (FIG. 5) encompassing the tip ends of lead regions 252.Such selective degradation may be provided, for example, by selectivelyapplying ultraviolet light or other radiation effective to degrade layer206. The tip ends of the leads are bonded to a further element 222 bythe conductive material carried on the tip ends. Here again, furtherelement 222 and wafer 200 are moved away from one another so as to bendthe leads towards a vertically extensive configuration. A curablematerial desirably is injected around the leads during or after themovement step. Components with lead regions, and assembly techniques foruse with such components, are disclosed in copending, commonly assignedU.S. patent application Ser. Nos. 09/140,589, filed Aug. 26, 1998; and09/317,675, filed May 24, 1999, the disclosures of which are herebyincorporated by reference herein. Other components which include leadswith polymeric layers are disclosed in U.S. Pat. Nos. 5,915,752 and5,536,909 the disclosures of which are hereby incorporated by referenceherein, and the aforementioned PCT/US96/14965 application.

[0060] As illustrated in FIG. 8 and 9, the vapor phase connection methoddiscussed above can be used to make more complex assemblies. Thus, acomponent 300 in accordance with another embodiment of the inventionincorporates numerous dielectric layers 302 and traces 304 extendingbetween these dielectric layers. Vertical conductors 308, desirablyformed by the vapor-phase process as discussed below, extend throughsome or all of these layers. At least some of the traces 304 andvertical conductors 308 are arranged in pairs or sets. The bottomsurface of body 300 has numerous leads 310. As best seen in FIG. 8, eachlead 310 includes a plurality of conductors 312 and 314, as well as adielectric layer 316 separating the conductors from one another. Theconductors 312 and 314 are connected to contacts 318 and 320 of asemiconductor device 322 such as a chip or wafer. The contacts 318 and320 connected to each lead desirably are adjacent one another and may beconnected to the same internal electronic device 324 disposed withinchip or wafer 322. As explained in greater detail in co-pending commonlyassigned U.S. patent application Ser. Nos. 09/140,589 and 08/715,571,filed Sep. 19, 1996; and 09/020,754, filed Feb. 9, 1998, and in PCTInternational Publication No. WO 97/11588, the disclosures of which areincorporated by reference herein, the use of traces and conductorsarranged in pairs or sets of plural traces or conductors provides acontrolled impedance signal path. For example, such a path mayincorporate a signal conductor and a ground conductor extendinggenerally parallel to one another, or may include a set of two or moresignal conductors extending generally parallel to one another. Asdiscussed in detail in these applications, a circuit 324 within the chipmay be arranged to transmit or receive oppositely directed pulses on aset of adjacent contacts such as contacts 318 and 320, so that thesepulses will be transmitted along the set of conductors 312 and 314 onthe same lead and transmitted along juxtaposed, parallel traces such astraces 304 a and 304 b (FIG. 8). As further described in theseapplications and publications, such an arrangement provides rapid,reliable signal transmission. Also, the controlled impedance signalpaths provided in this arrangement may be used to conduct signalsbetween different elements of chip or wafer 322, i.e., to conductsignals within a single chip or wafer. For example, traces 304 c and 304d and the associated leads 310 a and 310 b provide a low impedancesignal path between two widely separated electronic devices within chip322, as well as a path for conduction to external terminals 326.Provision of a low impedance signal path in turn allows rapidpropagation of signals between widely separated elements of the chip andsimplifies the task of routing signals within the chip. The ability ofthe present invention to form connections within small holes providesfor a particularly compact assembly. As best seen in FIG. 8, thevertical conductors may be formed within holes of different sizes andtypes. For example, a vertical conductor 332 is formed within hole 330extending through several polymeric layers, whereas another verticalconductor is formed at the hole overlying contact 320 and extendsthrough only the thickness of passivation layer 334. In a furthervariant, multiple chips are connected to a single component, such ascomponent 300, and interconnected by the conductors and leads to form amulti-chip module.

[0061] As seen in FIG. 10, the vapor phase connection process may beused within an assembly composed entirely of bodies formed from siliconor other semiconductor materials. Thus, a composite chip or wafer can bemade by stacking chips 400, 402, and 404. Chips 400 and 404 may containactive semiconductor electronic devices 405, whereas the middle chip 402may incorporate only insulating layers and conductors 406. Holes 408 inchip 402 may be aligned with contacts on the other chips and anevaporable conductive material may be evaporated within the holes insubstantially the same way as described above. The process ofevaporation may occur simultaneously with a process of fusion whichbinds the chips together and fuses the same into a solid unit. Forexample, such a process may occur at a relatively high temperature andmay involve the fusion of silicon or other elements at the matingsurfaces. Alternatively or additionally, such a fusion process mayinvolve activation of a high-temperature adhesive or a eutectic bondingmaterial.

[0062] Such a process can be used to fabricate assemblies of chips whereeach of the chips includes active device or, alternatively, where one ormore of the chips includes only conductors and passive device. This isparticularly useful where the production processes used to make thevarious chips are incompatible with one another. For example, traces 406may formed from a metal such as copper, gold, platinum or other metalswhich are difficult to deposit in conventional semiconductor fabricationprocesses or which have deleterious effects on active devices whenpresent in close proximity to the active devices. The vapor phaseconnection process serves to unite these conductors with electronicdevices 405 in chips 400 and 404. Although the conductors 406 areelectrically connected to the devices 405, the conductors remainisolated from the devices so that little or no diffusion of theconductor material into the devices occurs during fabrication or use.Stated another way, the connections formed by the vapor phase connectionprocess maintain chemical isolation.

[0063] Alternatively or additionally, chips 400 and 404 may be formed bymutually incompatible processes or formed from mutually incompatiblematerials as, for example, where chip 400 is formed from a compoundsemiconductor such as a III-V compound, a II-VI compound, or othercompound semiconductor and where chip 404 is formed principally fromsilicon. As used in this disclosure, the term “III-V” compound refers toa compound of any one or more of Al, Ga, In or Tl with any of N, P, As,Sb or Bi, whereas the term “II-VI compound” refers to a compound of anyone or more of Be, Mg, Ca, Sr, Ba, Zn, Cd, and Hg with one or more of O,S, Se and Te. Typically, these compound semiconductors also includedopants. In a further variant, the middle chip 402 is eliminated and theentire stack consists of only two chips. One or both of these chips hasholes and contacts aligned with the holes and the contacts on the twochips are joined to one another using an evaporable conductive materialas described above. The ability of the vapor phase conductor formingprocess to provide small vias is particularly useful where these viasare to be formed within a chip itself. A further advantage of using thepresent connection process to assemble plural layers of semiconductormaterial is that it allows parallel processing of the various layers.For example, one or more layers (typically layers incorporating activedevices) may be formed using a very fine line width, whereas anotherlayer or layers (typically incorporating only conductors and passivedevices) may be fabricated with a coarser line width. This allowsfabrication of the conductor layers using less expensive, more reliableand higher-yielding processes. Further, the ability to fabricate thelayers separately allows for testing of the individual layers beforeassembly.

[0064] As depicted in FIG. 11, an assembly according to a furtherembodiment of the invention includes a dielectric layer 500 having oneor more conductors 502 disposed adjacent a top surface. These conductorsextend predominantly in first or x direction. Dielectric element 500 hasholes 504 in the form of elongated slots extending generally in the xdirection beneath some portions of conductors 502. Another element suchas a dielectric layer or body 506 has conductors 508 extendingpredominately in a second or y direction transverse to and desirablyorthogonal to the first or x direction. Conductors 508 have elongatedmasses of conductive material 510 thereon. In the position illustratedin FIG. 11, bodies 500 and 506 are remote from one another. In a joiningprocess, the bodies are engaged with one another in the same manner asdescribed above and the conductive material 510 is evaporated so as toform a vertically extending conductor within each slot 504.

[0065] Use of elongated conductive elements and slots in this embodimenthelps to assure that a reliable connection will be made even if one orboth of the elements is slightly out of nominal positron. Thus, providedthat any point on slot 504 is aligned with any region of lead 508 havingthe evaporable conductive material, the connection will be made.Misalignment in the first or x direction will simply move the connectionslightly along the length of slot 504 and trace 502, whereasmisalignment in the y direction will simply move the interconnectionalong the lead 508. Tolerance sensitivity can be further reduced byproviding the evaporable conductive material within slot 504. In thiscase, so long as slot 504 intercepts some portion of lead 508, theconnection will be made. As discussed above, the vapor phase connectionprocess typically works best with relatively small holes. Thus, theminimum dimension or width w of the hole or slot 504 desirably is lessthan about 60 microns and more desirably 25 microns or less.

[0066] In a further variant, the chambers are formed by providingopenings in adhesive layers, so that the adhesive layer itself serves asthe dielectric element which cooperatively defines the chamber. Thus,the assembly shown in FIG. 12 includes several dielectric bodies 620.Each dielectric body includes traces 602 extending on its top surfaceand traces 604 extending on its bottom surface. Traces 602 on all bodiesother than the topmost body 620 a are provided with an evaporableconductive material over their entire surfaces. Adhesive layers 625 areprovided on the top surfaces of the dielectric bodies other than thetopmost body. These adhesive layers cover traces 602. Prior tolaminating the layers, the adhesive is removed selectively to form holes622 over traces 602 only at those locations where connections are to beformed. For example, the adhesive may be removed by laser ablation or byselective treatment with a solvent using a mask to protect areas whichare not to be removed. The layers are then laminated. Adhesive layers625 hold bodies 620 together, and insulate the traces 602 on the top ofeach dielectric layer from the traces 604 on the bottom surface of thenext adjacent layer except at locations where holes are provided in theadhesive layers. Holes 622 in the adhesive layers form chambers betweenthe bodies 620. The evaporable conductive material on traces 602 atholes 622 can be evaporated and deposited within these chambers to formconductive connections to the traces 604 in the same manner as discussedabove. The holes formed in the adhesive layers may have any of theconfigurations discussed above, such as round holes or elongated slots.

[0067] In a further variant, the adhesive layers may be provided inseparate, self-supporting elements, referred to herein as “interposers.”Each such interposer may consist entirely of the adhesive. Moretypically, each interposer may include one or more sublayers such asstructural reinforcements, electrically conductive elements or both,with the adhesive being disposed on opposite sides of thereinforcements. Merely by way of example, the interposers may includeinternal structures as shown in commonly assigned U.S. Pat. Nos.5,367,764 and 5,282,312, the disclosures of which are herebyincorporated by reference herein. For example, an interposer 725depicted in FIG. 13 includes a dielectric reinforcing layer 726 andlayers of adhesive 727 and 728 on oppositely-facing top and bottomsurfaces of the reinforcing layer, so that the adhesive layers definethe first surface 731 and second surface 733 of the interposer. Holes730 extend through all of these layers. Bodies 740 and 742 are laminatedto the first and second surfaces, respectively, of the interposer.Conductive elements 744 on body 740 and conductive elements 746 on body740 are aligned with holes 730 and thus exposed to the holes adjacentopposite ends of each hole. The conductive elements, bodies andinterposer cooperatively define chambers in substantially the samemanner as discussed above. A conductive material is provided within eachsuch chamber, also in the same manner as discussed above. For example,one or both of the conductive elements may bear the conductive material.The conductive material is evaporated within the chambers as describedabove, so as to form electrical conductors extending between theconductive elements associated with each hole. In a further variant, theinterposers may include metallic sheets having holes therein anddielectric material coated on the metallic sheets and lining the holesas disclosed, for example, in certain embodiments of U.S. Pat. No.5,590,460 the disclosure of which is hereby incorporated by referenceherein. The coating may be performed selectively so as to leave theconductive sheet uncoated in the interiors of at least some of theholes. Electrical connections to the conductive sheet will be formedwhen the conductive material is dispersed in such holes as discussedabove with reference to hole 28 b, FIG. 1.

[0068] In the processes discussed above, the conductive material isdispersed by conversion to a gaseous phase through application of heat,and deposited from the gaseous phase onto the walls of the holes so asto form the conductors. However, other methods of dispersing theconductive material within the chambers may be employed. For example,energy may be supplied to promote dispersion of the conductive materialby application of an electromagnetic, acoustical or radiant energy as,for example, by inductive or microwave heating or a irradiation of theassembly with visible or infrared light or other radiant energy.

[0069] Mechanical energy in the form of ultrasonic or sonic vibrationmay be applied to the assembly, with or without separate heat input.Such sonic energy may cause evaporation of the conductive material, ormay physically disperse the conductive material within the holes withoutevaporation. For example, the applied energy may be effective to convertthe conductive material to a liquid phase, and to atomize the resultingliquid mass, thereby forming a mist of conductive material within eachchamber. Even where a mist is not formed, the applied energy may movethe liquid about within the chambers, thereby spreading the liquidwithin the chambers and onto the walls of the chambers. Mechanicalenergy also may be applied by vigorously shaking and/or tumbling theassembly. In the liquid-phase spreading processes, as well as in theevaporation processes discussed above, energy applied to the conductivematerial within the chambers is effective to spread the conductivematerial by mechanisms which do not rely on wetting of the interiorsurfaces of the chambers. In those embodiments where the conductivematerial can be spread as a liquid, evaporation of the conductivematerial is not essential. Therefore, the conductive material need notbe evaporable. The term “dispersible conductive material” as used hereinincludes both evaporable conductive materials and materials which can bedispersed in the liquid phase by application of energy.

[0070] It is not essential to apply either mechanical energy or heat tothe entire assembly at the same time. For example, as shown in FIG. 14,an ultrasonic energy applicator 800 driven by a conventional ultrasonicvibration source (not shown) is swept in a direction of movement Macross one surface of the assembly while the opposite surface issupported on a support 802. The applicator thus applies ultrasonicenergy to various sections of the assembly seriatim, so that conductorsare formed in different holes at different times. In the position shown,conductors have already been formed in holes 804; conductors are beingformed in holes 806; and conductors have yet to be formed in holes 808.A localized heating device or a beam of radiant energy can be swept overthe assembly in the same way. Also, more complex sweep patterns such asraster scanning with or without momentary dwell at locations where theenergy is directed onto holes may be employed. The relative motionbetween the energy applicator and the assembly may be imparted by motionof the assembly, by motion of the applicator, or both. For example, asseen in FIG. 15, heat, ultrasound or other energy may be applied througha pair of rollers 822 which cooperatively define a nip therebetween. Theassembly is advanced through the nip by rotation of the rollers asindicated by arrows R. The rollers apply pressure on the surfaces of theassembly, and also apply energy to the region of the assembly which ismomentarily disposed between the rollers.

[0071] In the embodiments discussed above, the dispersible conductivematerial is provided in the form of a metal and does not changecomposition during the process. However, a conductive material may beprovided within the closed chambers by providing one or more materialswhich decompose or otherwise react to yield a metal or other conductivematerial which disperses within the chamber and deposits on the walls ofthe chamber. The term “conductive material precursor” is used in thisdisclosure to refer to such materials. A conductive material precursormay be provided as a single component or as multiple components whichare mixed with one another within the chambers. Some conductive materialprecursors include, for example, metal hydrides, metal azides and metalacetates. The reaction may occur in the vapor phase or in a liquidphase.

[0072] In the embodiment discussed above with reference to FIGS. 8 and9, a semiconductor device such as a chip or wafer is connected toanother element through leads. In a further variant, the invention canbe employed to make connections between a semiconductor device andanother element without the use of leads. As shown in FIG. 16, asemiconductor device 900 such as a chip or wafer having a front surface902 and contacts 904 on such front surface is mounted to a substrate 906having contact pads 908 on a top surface 909. Device 900 is mounted tothe substrate by a dielectric layer 910 having holes 912 therein. Thefront face 902 of the semiconductor device faces toward the top surface909 of the substrate. The holes 912 are aligned with contacts 904 andpads 908. Dielectric layer 910 may include adhesives, and may beprovided in any of the ways discussed above. For example, the layer maybe applied as a coating on the device or on the substrate, and holes 912may be formed in registration with the contacts or pads. Here again,when the parts are assembled, the holes form chambers with conductiveelements exposed therein. A dispersible conductive material or aconductive material precursor is provided within each chamber, andenergy is applied so as to disperse the conductive material or react theprecursor and thereby deposit conductive material on the interiors ofholes 912 and form conductors 914 extending between contacts 904 andpads 908.

[0073] As these and other variations and combinations of the featuresdiscussed above can be utilized without departing from the invention,the foregoing description of the preferred embodiments should be takenby way of illustration rather than by way of limitation of the inventionas defined by the claims.

1. A component for making connections in a microelectronic assembly comprising: (a) a dielectric layer having first and second surfaces; (b) a plurality of elongated conductors on said first surface; and (c) slots in said dielectric layer extending through the layer beneath said conductors, said slots extending in the direction of elongation of said conductors.
 2. A component as claimed in claim 1 further comprising a dispersible conductive material disposed in said slots. 